1. Technical Field
The present invention relates to a display device, and more particularly, to an IPS type liquid crystal display device having excellent visibility angle characteristic.
2. Description of Related Art
A liquid crystal display panel used in a liquid crystal display device has a Thin Film Transistor (TFT) substrate, on which pixels each having a pixel electrode and a thin film transistor and the like are formed in matrix, and an opposite substrate facing the TFT substrate, on which color filters and the like are formed in positions corresponding to the pixel electrodes of the TFT substrate, and a liquid crystal held between the TFT substrate and the opposite substrate. An image is formed by controlling light transmittance through a liquid crystal molecule by pixel.
Since the liquid crystal display device is a flat and light-weight device, it is widely used in various fields. A small liquid crystal display device is used in many cellular phones and Digital Still Cameras (DSCs). The liquid crystal display device has a problem in its visibility angle characteristic. The visibility angle characteristic is a phenomenon that the luminance varies or chromaticity varies in accordance with view from front or diagonal direction. The visibility angle characteristic is excellent in In Plane Switching (IPS) method of operating a liquid crystal molecule with a horizontal direction electric field.
Various types of IPS methods exist; however, a main stream method is forming a common electrode or pixel electrodes solidly over a flat surface, arranging comb-shaped pixel electrode or common electrode on the common electrode, with an insulating film therebetween. The liquid crystal molecule is rotated with an electric field which occurs between the pixel electrode and the common electrode. With this method, the transmittance can be increased.
Conventionally, in the above IPS method, first, a TFT is formed, then the TFT is covered with a passivation film, then, the above-described common electrode, the insulating film, the pixel electrodes and the like are formed on the film. However, since there is a requirement for manufacturing cost reduction, the number of layers of the conductor film, the insulating film and the like in the TFT substrate is reduced.
As an example of another IPS method, Japanese Published Unexamined Patent Application No. 2009-168878 discloses forming a common electrode on the same layer of a gate electrode, and forming a comb-shaped pixel electrode, with a gate insulating film and a protective insulating film therebetween.
The pixel electrode is supplied with a video signal via the TFT. To prevent variation of the video signal in accordance with ON/OFF of gate voltage of the TFT, added capacitance is applied. In the conventional IPS, a comb-shaped pixel electrode and the common electrode, in nest relation, are used on the same flat surface. Japanese Published Unexamined Patent Application No. 2003-207796 discloses a structure of such IPS method using a top gate type TFT, in which a common electrode is formed to oppose an n+ region of a TFT semiconductor layer, with an inter-layer insulating film therebetween, with respect to the n+ region of the TFT semiconductor layer, so as to increase the added capacitance.
FIG. 10 is a plan view of an IPS pixel structure of the present invention. In FIG. 10, a pixel is formed in a region surrounded by a main scan line 10 and a video signal line 20. A TFT is formed on the main scan line 10. That is, a semiconductor film 105 is formed via a gate insulating film 103 on the main scan line 10, and a drain electrode 106 and a source electrode 107 are formed on the semiconductor film. The main scan line 10 is also used as a gate electrode. As shown in FIG. 11, in the present pixel structure, a pixel electrode 101 connected to the source electrode 107 of the TFT is formed in the bottom layer, while a common electrode 111 is formed in the top layer, to drive a liquid crystal molecule 200 with a voltage between the pixel electrode 101 and the common electrode 111.
FIG. 11 is a B-B cross sectional view of FIG. 10. In FIG. 11, a gate electrode 102 and the pixel electrode 101 are formed on the glass TFT substrate 100. The gate electrode 102 is an Al and AlMo alloy laminated layer film. The pixel electrode 101 is formed with Indium Tin Oxide (ITO). The gate insulating film 103 is formed so as to cover the gate electrode 102 and the pixel electrode 101.
An e-Si semiconductor film 105 is formed on the gate electrode 102 and the gate insulating film 103, and the drain electrode 106 and the source electrode 107 are formed on the semiconductor film. The source electrode 107 is connected to the pixel electrode 101 via a first through hole 104 formed in the gate insulating film 103. An inorganic passivation film 109 is formed to cover the drain electrode 106 and the source electrode 107. The common electrode 111 is formed on the inorganic passivation film 109. The common electrode 111 has a slit 112. When a voltage is applied between the pixel electrode 101 and the common electrode 111, an electric line of force occurs through the slit 112, to rotate the liquid crystal molecule 200, to control the quantity of light passing through a liquid crystal layer. In this manner, the IPS method, to which the present invention is applied, is very different from the structure of the liquid crystal display devices disclosed in the above-described Japanese Published Unexamined Patent Application Nos. 2009-168878 and 2003-207796.
FIG. 11 shows a structure where the number of layers is small and the number of photolithographic processes is small. This is an excellent structure in view of manufacturing cost. On the other hand, when added capacitance is formed between the pixel electrode 101 and the common electrode 111 to suppress voltage shift due to variation of gate voltage in the TFT, it is difficult to increase the added capacitance.
That is, in FIG. 11, the added capacitance is formed between the pixel electrode 101 and the common electrode 111, and the gate insulating film 103 and the inorganic passivation film 109 exist between the pixel electrode 101 and the common electrode 111. The gate insulating film 103, having a thickness of about 240 nm, and the inorganic passivation film 109, having a thickness of about 500 nm, are both formed with SIN. In this manner, since the added capacitance is formed via the insulating film having the total thickness of 740 nm, the added capacitance cannot be sufficiently increased. Accordingly, there is a problem of influence on the pixel voltage based on the ON/OFF of the gate voltage.